1. Field of the Invention
The present invention relates to a compound semiconductor switch circuit device, and more particularly relates to a compound semiconductor switch circuit device which suppresses a leak of a high-frequency signal and prevents deterioration of distortion characteristics.
2. Description of the Related Art
In a compound semiconductor switch circuit device for which a high power is required, a switching element having a plurality of FETs (Field Effect Transistor) connected to each other in series is adopted. This technology is described for instance in Japanese Patent Application Publication No. 2004-254086 (see FIG. 4).
FIG. 18 shows a Switch MMIC (Monolithic Microwave Integrated Circuit) including two switching elements having a plurality of FETs connected to each other in series, as an example of a conventional compound semiconductor Switch MMIC chip.
On a compound semiconductor substrate, two FET groups to be first and second switching elements SW1 and SW2 are disposed. In each of the FET groups, three FETs are connected in series. A first control resistor CR1 and a second control resistor CR2 are connected, respectively, to six gate electrodes included in the respective FET groups. Moreover, electrode pads I, O1 and O2, which are connected to a common input terminal IN and output terminals OUT1 and OUT2, respectively, and two electrode pads C1 and C2, which are connected to control terminals Ctl1 and Ctl2, respectively, are provided in a periphery of the substrate.
A wiring formed of a second metal layer indicated by a dotted line is a gate metal layer 220 which forms the gate electrodes of the respective FETs. In addition, a wiring formed of a third metal layer indicated by a solid line is a wiring metal layer 230 which connects the respective elements to each other and forms the pads. Moreover, an ohmic metal layer, which is a first metal layer and comes into ohmic contact with the substrate, forms source and drain electrodes of the respective FETs, and the like. The ohmic metal layer is not shown in FIG. 18 because the ohmic metal layer is overlapped by the wiring metal layer.
In FET1-1 of the first switching element SW1, three comb-shaped wiring metal layers 230 extended downward are source electrodes 215 (or drain electrodes) which are connected to the common input terminal pad I. Below the source electrodes 215, source electrodes (or drain electrodes) are provided, which are formed of the ohmic metal layer. The respective source electrodes 215 are connected to each other by a source wiring 231 formed of the wiring metal layer 230.
Moreover, three comb-tooth-shaped wiring metal layers 230 extended upward are drain electrodes 216 (or source electrodes) of FET1-1. Below the drain electrodes 216, drain electrodes (or source electrodes) are provided, which are formed of the ohmic metal layer. The respective drain electrodes 216 are connected to each other by a drain wiring 232 formed of the wiring metal layer 230.
The source electrodes 215 and the drain electrodes 216 are disposed so as to have a shape formed by engaging comb teeth with each other. Between the source and drain electrodes, five comb-tooth-shaped gate electrodes 217 are disposed, which are formed of the gate metal layer 220. The respective gate electrodes 217 are connected to each other by a gate wiring 221 outside an operation region 300 indicated by a dashed line.
In the Switch MMIC described above, a leak of a high-frequency analog signal (hereinafter referred to as a high-frequency signal) occurs between the source and drain electrodes in a spot where the both electrodes are close to each other. Thus, there is a problem that electrical characteristics are deteriorated by the leak.
To be more specific, in the case where the first switching element SW1 is set to be an on-side switching element, the high-frequency signal is transmitted to the first output terminal pad O1 after passing through a channel region of each FET from the common input terminal pad I as indicated by the arrow.
In the second switching element SW2 to be an off-side switching element, an X region surrounded by a chain double-dashed line is exposed to a high-power high-frequency signal since the region is closest to the common input terminal pad I. However, in the X region, no leak of the high-frequency signal occurs. Moreover, on a signal path between the common input terminal IN and the first output terminal OUT1 on the on side, designed values for linearity characteristics of an output signal can be ensured.
However, it was found out that, in a spot where the source and drain electrodes are adjacent to each other and directly face each other in the high-power switch circuit device constituted by the switching element including the plurality of FETs connected to each other in series, the leak of the high-frequency signal occurs outside the channel region of the FET.
Specifically, in Y regions indicated by solid lines, where the source and drain electrodes are adjacent to each other and directly face each other, the leak of the high-frequency signal occurs between the source and drain electrodes (to be more specific, between the source electrodes 215 and the drain wiring 232 and between the source wiring 231 and the drain electrodes 216). Thus, there is a problem that designed values for a distortion level of the output signal cannot be ensured and a harmonic wave level is too high.
FIG. 19 shows another pattern of the conventional Switch MMIC shown in FIG. 18. In the Switch MMIC shown in FIG. 18, the gate wiring 221 is disposed on the side of the common input terminal pad I with respect to the comb-tooth-shaped gate electrodes 217. Moreover, tips of the comb-tooth-shaped gate electrodes 217 are disposed on the side of the first and second output terminal pads O1 and O2.
Meanwhile, in a Switch MMIC shown in FIG. 19, a gate wiring 221 is disposed on the side of first and second output terminal pads O1 and O2 with respect to comb-tooth-shaped gate electrodes 217. Moreover, tips of the comb-tooth-shaped gate electrodes 217 are disposed on the side of a common input terminal pad I. Since other constituent components are the same as those described above in FIG. 18, description thereof will be omitted.
In the pattern of FIG. 19, when a second switching element SW2 is on an off side, despite the fact that an X′ region closest to the common input terminal pad I is exposed to a high-power high-frequency signal, source and drain electrodes are adjacent to each other and directly face each other. Thus, it was found out that a large leak of the high-frequency signal occurs in the X′ region. To be more specific, on a signal path between a common input terminal IN and a first output terminal OUT1 on an on side, only Pin0.1 dB, which is lower than the designed value by a few dB, can be secured. Moreover, there is a problem that the leak of the high-frequency signal occurs between the source and drain electrodes also in a Y region and distortion characteristics are also poor.